1. Field of the Invention
The present invention relates to a system for controlling multiple common memories which are commonly owned and used by a plurality of processor units for improving reliability.
2. Description of the Prior Art
The basic arrangement of common memories is found in a dual common memory system, in which two memories are used in common by a plurality (N) of processing units, as shown in Japanese Patent Application Public Disclosure No.58-16362 (hereinafter referred to as "Prior Art 1").
On the other hand, an example of commonly using N common memories by N processing units is given in Japanese Patent Application Public Disclosure No.57-189257 (hereinafter referred to as "Prior Art 2"). These prior art structures have following drawbacks:
As for "Prior Art 1", it is likely that a plurality of processing units access each of the two common memories at a time, and, accordingly, each and every processing unit is compelled to wait for its turn for a relatively longer time, thereby causing a decrease of processing efficiency. Also, disadvantageously, the physical distance from each processing unit to the common memories will increase with the increase of the number of the processing units, and, accordingly, the time involved for accessing a selected common memory becomes much longer.
As for "Prior Art 2", each processing unit has its own common memory, and, accordingly, the cost of production will increase. If selected ones of all the processing units are front-end processors dedicated for inputting or outputting, or if selected processing units are of conventional types, it is difficult to provide each of such selected processing units with a common memory of the same capacity in view of cost, mounting space and compatibility or interchangeability.
As for a common memory addressing system, the same addresses are used in common among the plurality of processing units in Prior Art 1 and 2. Assume that it is desired that the function of a program is expanded. If the content of a selected table contained in the common memory should be increased, the addresses of the tables which follow the selected table must be shifted. Therefore, all CPUs (central processing units) must be stopped simultaneously, and the program of each and every CPU must be reconstructed. Therefore, the on-line (non-stop) expansion of the function is difficult in the system using common memories.